Here is a tutorial to help you dump simulation signals to the waveform viewer for debugging from the hierarchy navigator.

Step 1: Open up LogicSim
Step 2: File->New Project
Step 3: Enter "myproject" for project name and "mytopmodule" for top module when prompted, choose your desired location to save the project.

Step 4: File->New->Verilog, choose "Yes" when prompted "Add file to project?"
Step 5: Enter "wavedump.v" when prompted to save the new file
Step 6: Copy and paste the following code into the "wavedump.v" code editor

module mytopmodule();
reg osc;
reg [10:1] vec_reg;
wire tmp1, tmp2, tmp3;
integer num;
real real_val;
reg [10:0] tmp14, tmp15, tmp16;
reg tmp4, tmp5, tmp6;
reg [20:0] tmp24, tmp25, tmp26;

initial
begin

osc = 0;
vec_reg = 0;
num = 10;
real_val = 100;

repeat(20)
begin

$display("osc=%b", osc);
#20

osc = ~osc;
vec_reg = ~vec_reg;
num = num + 2;
real_val = real_val + 10;

end

end

endmodule

Step 7: File->Save File
Step 8: Simulation->Load Simulation
Step 9: Right-click on "mytopmodule" in the "Hierarchy" pane, choose "Add To Waveform", choose "Yes" when prompted "Add file to project?"
Step 10: Enter "wavedump.wave" when prompted to save the new file
Step 11: Simulation->Run Simulation, choose "Yes" when prompted "Save changes to wavedump.wave ?"

LogicSim will dump simulation signals of the selected module instance to the waveform viewer. Shortly, you will see values of selected signals being displayed on the waveform viewer after the simulation run is completed.

Last Updated: 20 Apr 2007
Date Created: 21 Jan 2007