Here is a tutorial to help you create a simple simulation project. This project will display a simple "Hello World!" text when simulated.

Step 1: Open up LogicSim
Step 2: File->New Project
Step 3: Enter "myproject" for project name and "mytopmodule" for top module when prompted, choose your desired location to save the project.

Step 4: File->New->Verilog, choose "Yes" when prompted "Add file to project?"
Step 5: Enter "hello_world.v" when prompted to save the new file
Step 6: Copy and paste the following code into the "hello_world.v" code editor

module mytopmodule();

initial
begin

$display("Hello World!");

end

endmodule

Step 7: File->Save File
Step 8: Simulation->Load Simulation
Step 9: Simulation->Run Simulation

LogicSim will simulate the project given the top module "mytopmodule" as the entry point. Shortly, you will see "Hello World!" printed on the output pane of the workspace.

Last Updated: 20 Apr 2007
Date Created: 21 Jan 2007