Here is a simple tutorial to help you create a simple "Hello World!" simulation in Verilog using LogicSim.

Step 1: Open up LogicSim
Step 2: File->New->Verilog

Step 3: Copy and paste the following code into the code editor:

module hello_world();

initial
begin

$display("Hello World!");

end

endmodule

Step 4: File->Save File, save as "hello_world.v"
Step 5: Simulation->Auto Simulate, select hello_world.v simulation file

LogicSim will auto select a top module for you. Shortly, you will see "Hello World!" printed on the output pane of the workspace.

Last Updated: 20 Apr 2007
Date Created: 1 Dec 2006