LogicSim Workspace 1
LogicSim is an affordable and user-friendly Verilog simulator for ASIC and FPGA design verification. It delivers a powerful and easy-to-use graphical user interface that lets you quickly simulate your Verilog designs.

LogicSim Workspace 2
This latest release offers a new and powerful simulation technology that simulates big designs faster. And the new Microsoft Visual Studio style workspace makes working with complex, multi-file designs a snap

Code Editor
Create, edit and read simulation source code files with our powerful HDL editor, supporting syntax highlighting for Verilog, SystemVerilog, VHDL, and SystemC languages

Customize Code Editor
Code option dialog allows you to customize keyword color, background color, string color, comment color, and many more. Offering you customized look-and-feel according to your personal preferences.

Waveform Viewer
Debug and trace simulation signals with our user-friendly waveform viewer.

Customize Waveform Viewer
Waveform option dialog allows you to customize signal color, background color, signal name color, time bar color, node hierarchy level, and many more. Offering you customized look-and-feel according to your personal preferences.

Command-Line LogicSim
Run your regression tests with command-line LogicSim, which offers higher performance throughput and lower memory consumption, compared to its GUI counterpart.

Third-Party API
It also offers seemless integration with external IDE, such as Eclipse, Debussy, VeritoolsDesigner, and so on, via LogicSim third-party API.

Full-Screen Mode
Edit and view document with workspace full-screen mode.

Setting Breakpoints
Pause simulation run with simulation breakpoints.

Custom Code Editor
Customize code editor look-and-feel according to your personal preferences.

Custom Waveform Viewer
Customize waveform viewer look-and-feel according to your personal preferences.

Hierarchy Navigator
Locate source code line from hierarchy navigator.

Breakpoint Manager
Manage simulation breakpoints from breakpoint manager.

Simulation Settings
Save and load persistent simulation settings.

Waveform Radix Conversion
Convert waveform signals to any radix format on the fly; supporting ASCII, binary, decimal, hexadecimal, octal, and unsigned radix conversion.

Output Pane
Display simulation messages to workspace output pane.

Object Browser
Browse internal module signals with object browser.

Export VCD to GTKWave
Export or dump VCD waveform for debugging with third-party waveform viewers, such as GTKWave, nWave, and Undertow.