Today automated design verification plays a vital role in many ASIC and FPGA projects. Automated verification has long been thought critical for large IC development organizations, but is often considered to be too expensive and difficult to implement for smaller companies. Zeemz's LogicSim breaks this stereotype.

LogicSim is an affordable and user-friendly Verilog simulator for ASIC and FPGA design verification. It delivers a powerful and easy-to-use graphical user interface that lets you quickly simulate your Verilog designs. It's built on our state-of-the-art single kernel simulation engine MULCORED™ (Multi-Core Event Distribution) technology, in one easy-to-use and totally integrated package at an affordable price.

Verilog simulator and debugger, supporting full IEEE 1364-2001

Verify behavioral and RTL models with functional simulation

Verify pre/post-layout gate-level netlist with SDF back-annotation timing simulation

Debug and trace simulation signals with user-friendly waveform viewer

Create Verilog, SystemVerilog, VHDL, and SystemC source code with powerful HDL editor

Export VCD waveform to third-party waveform viewers

Fast RTL simulation speed, supporting multi-million gate designs

Save design verification time, dramatically reduce ASIC and FPGA development time

Easy-to-use and powerful user interface, ease verification debugging pain

The most affordable and complete logic simulator, offering FREE LIFETIME UPGRADE

This latest release offers a new and powerful simulation technology that simulates big designs faster. And the new Microsoft Visual Studio style workspace makes working with complex, multi-file designs a snap. So what are you waiting for? Let's make your purchase now!

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If you have questions on LogicSim, or need further assistance, feel free to write to us.