LogicSim 3.3 Key Features
LogicSim is an affordable and user-friendly Verilog simulator for ASIC and FPGA design verification. It delivers a powerful and easy-to-use graphical user interface that lets you quickly simulate your Verilog designs. It's built on our state-of-the-art single kernel simulation engine MULCORED™ (Multi-Core Event Distribution) technology, in one easy-to-use and totally integrated package at an affordable price.
LogicSim is undoubtedly the most feature rich and complete Verilog simulator available on the market today - at any price. But don’t just take our word for it. Read the features listed below and judge for yourself.
Simulate your designs with the latest and most advanced Verilog constructs supported in the Verilog IEEE 1364-2001 LRM. LogicSim supports the following Verilog constructs:
- Data Types: reg, wire, wand, wor, tri, triand, trior, tri0, tri1, trireg, supply, supply0, supply1, integer, real, realtime, time, signed, unsigned, vector, memory, parameter, localparam, and many more.
- Operators: concatenation, replication, arithmetic, modulus, relational, logical, case, bit-wise, reduction, shift, conditional, and many more.
- Expressions: constant, bit-select, part-select, array element, mintypmax, function call, and many more.
- Statements: blocking assignment, non-blocking assignment, assign/deassign, force/release, disable, if-then-else, case, casex, casez, sequential block, parallel block, event trigger, event control, delay control, task enable, and many more.
- Switches: and, nand, nor, or, xor, buf, bufif0, bufif1, not, notif0, notif1, pulldown, pullup, cmos, nmos, pmos, rcmos, rnmos, rpmos, rtran, rtranif, rtranif0, rtranif1, tran, tranif0, tranif1, and many more.
- Generates: generate assign, generate case, generate if-then-else, generate for, genvar, and many more.
- Blocks: module, primitive, table, always, initial, task, function, specify, and many more.
- System Functions/Tasks: $bits, $display, $dumpvars, $fgets, $fopen, $fread, $monitor, $random, $readmemb, $stop, $time, $write, and full list here.
- Timing Checks: $setup, $hold, $setuphold, $recovery, $removal, $recrem, $skew, $timeskew, $fullskew, $width, $period, and many more.
LogicSim is based on our state-of-the-art single kernel simulation engine MULCORED™ (Multi-Core Event Distribution) technology, is the result of many years of R&D effort layered upon our vast experience in logic simulation and design verification. It not only offers an unparalleled cost-performance point for RTL and gate-level simulation, but also lays the foundation for our future solutions.
Verify pre/post-layout gate-level netlist with SDF back-annotation timing simulation. Our advanced timing simulation engine allows annotation of library cell delays generated by ASIC and FPGA timing analysis tools into gate-level netlists. In addition, it will also annotate delays into Verilog timing checks, offering the most accurate and comprehensive timing verification solution via simulation.
Export VCD waveform to third-party waveform viewers, such as WaveProbe, GTKWave, nWave, and Undertow. LogicSim allows specifying grouped or ungrouped net buses, providing greater flexibility and control over the outputs of VCD dump files. All VCD dump files are in plain ASCII text files, can even be viewed in a simple text editor.
Our advanced timing simulation engine allows specifying of desired timing delay model. The default inertial delay mode annotates nets or ports with the specified delays; all scheduled events on the object are removed before delays are scheduled. On ther other hand, optional transport delay mode annotates nets or ports with the specified delays; all scheduled events on the object for times later than delays are removed. Together, offering the most accurate and comprehensive timing verification solution via simulation.
Debug and trace simulation signals with our user-friendly waveform viewer. Convert waveform signals to any radix format on the fly; supporting ASCII, binary, decimal, hexadecimal, octal, and unsigned radix conversion. Waveform option dialog allows customization of signal color, background color, signal name color, time bar color, node hierarchy level, and many more. Offering customized look-and-feel according to personal preferences.
Create, edit and read simulation source code files with our powerful HDL editor, supporting syntax highlighting for Verilog, SystemVerilog, VHDL, and SystemC languages. It supports simulation breakpoints setting directly in the source code files for real-time simulation pausing and debugging. Search text or locate file line number with our robust built-in text search engine. Code option dialog allows customization of keyword color, background color, string color, comment color, and many more. Offering customized look-and-feel according to personal preferences.
Run regression tests with command-line LogicSim, offering higher performance throughput and lower memory consumption, compared to GUI-based simulation. It will offer seemless integration with external IDE, such as Eclipse, Debussy, VeritoolsDesigner, and so on, via LogicSim third-party API.
Simulate and debug designs in a comfortable integrated development environment. Our
new multi-tabbed IDE allows navigation through module hierarchy and HDL files hassle-free. The workspace provides a cutting-edge look-and-feel that's similar to that of Microsoft's award-winning IDE Visual Studio 2005, this makes working with complex, multi-file designs a snap.
Set simulation breakpoints in code editor, and the simulator will pause based on specified breakpoint conditions. While pausing, it allows control of simulation by single stepping through source code statements. Our built-in breakpoint manager allows adding, locating and removing simulation breakpoints so easily.
Browse simulation design hierarchy with user-friendly hierarchy navigator. It allows easy navigation through complex design, locating source code line, and adding simulation signals to the waveform viewer. It resembles the "Class View" pane of Microsoft's award-winning IDE Visual Studio 2005, this makes working with complex, multi-file designs a snap.
Display internal signals of any module instance with object browser, allowing adding of individual signal instead of the entire module instance to the waveform viewer. Dynamic update and synchronization with hierarchy navigator whenever a module instance is selected.
Develop custom GUI shell to integrate with LogicSim using our exported API commands. Third-party software integration can be done with any programming interface that supports standard I/O stream pipe, such as Win32 ::CreateProcess API call.
Our complete software documentation is all available online, so that it can be accessed anywhere, anytime, and always up-to-date. As a registered customer, you can contact our help desk center, where you will get priority customer support. We reponse to all our customers within 24 hours, 24x7. Excellent and prompt customer service are an integral part of our business.
Every purchase of a new LogicSim license comes with FREE LIFETIME UPGRADE , yes 100% free. You can continue receiving free upgrade for life. You own a perpetual license for the free upgrade as well.
LogicSim can be installed and run on Microsoft Windows XP and above. All our software has been fine-tuned specially for Windows platform, so giving you maximum performance and usability that you can't find in any other simulation software. LogicSim is the only Verilog simulator that takes full advantage of Windows native GUI API, hence giving you responsive and cutting-edge user-experience. On the other hand, simulators such as ModelSim, VCS, and NC-Sim, are all developed using cross-platform toolkits, hence trading off portability with unresponsive, unstable, non-native, slow, and outdated user-interface.
With so many tools and features, so what are you waiting for? Let's make your purchase now!
If you have questions on LogicSim, or need further assistance, feel free to write to us.
