LogicSim Documentation
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- Getting Started
- Graphical IDE
- Code Editor
- Waveform Viewer
- Command-Line
- Supported Verilog System Functions/Tasks
- Unsupported General Features
- Unsupported Verilog IEEE 1364-2001 Features
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Once you have downloaded and installed the 30-day free trial, you can start using it without any limitation. All of our trial products are fully functional without any feature limitation or performance slowdown, however purchase is required upon 30-day expiry date.
You need both a valid email address and an activation key to activate LogicSim, as the activation key is generated based on your email address. The email address you supply during registration will act as your account with Zeemz, as all your future free upgrade, help support and communications will require this email address, so please remember it.
LogicSim can currently be installed on any Windows machines, starting from Windows XP onwards. We will only accept support requests for Windows XP or higher.
LogicSim comes in both GUI (glsim.exe) and command-line (lsim.exe). The former is a shell sitting on top of the latter.
The GUI is suitable for working with large projects with many files, as the workspace will handle all tedious command interactions with the kernel for you. The workspace also provide useful debugging tools, such as module hierarchy navigator, object browser, code editor and waveform viewer, which can't be found in command-line.
The command-line is useful for running regression tests, or in a scripted environment. LogicSim will offer higher performance throughput and lower memory consumption, when run in command-line.
To use LogicSim in command-line, you must add the installation path to your PATH environment variable, which shall be added by the installer by default. Thereafter, type "lsim" at the command prompt.
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LogicSim provides a workspace style integrated development environment with multi-tabbed windows, similar to that of Microsoft Visual Studio. It is suitable for working with large projects with many files, as the workspace will handle all tedious command interactions with the kernel for you.
The workspace provides useful debugging tools such as hierarchy navigator, breakpoint manager, object browser, code editor and waveform viewer, which can't be found in command-line.
To quickly simulate a design, select "Simulation->Auto Simulate" from the menu and select the source code files to simulate. LogicSim will automatically select a top-module for the simulation, so the user do not need to specify.
A top-level module is the top most module that instantiates the rest of the modules, and usually do not have any ports, and is also the entry point to the simulation.
You can use this feature to select multiple source files, however only Verilog source code files are supported at the moment.
Using auto-simulate has the same effect as command-line simulation, whereby no debugging information and overhead will be created, therefore higher performance throughput and lower memory consumption.
A project file contains all simulation settings pertaining to a simulation session. These simulation settings are saved into a persistent storage and will be remembered when loaded the next time.
To create a new project, select "File->New Project" from the menu and enter the project name, top-level module name and project location when prompted.
The project name can be anything, whereas the top-level module is the top most module that instantiates the rest of the modules, and usually do not have any ports, and is also the entry point to the simulation.
You can open any existing LogicSim project by selecting "File->Open Project". LogicSim project file ends with "lpf" file extension.
To customize the simulation settings, select "Project->Settings" from the menu . The following explains what each setting does.
| Simulation Setting | Description |
|---|---|
General -> Top Module |
Specify the top module for the simulation, and you must specify only 1 top module. A top-level module is the top most module that instantiates the rest of the modules, and usually do not have any ports, and is also the entry point to the simulation. |
Verilog -> Additional Include Paths |
Specify additional include path(s) for the simulation. An include path is the lookup path used when an include compiler directive such as `include is used. The default path is the current working directory if none is specified. Use this option if you want the compiler to look in additional include path if the include file is not found in your default path. |
Verilog -> Timing Case |
Specify the timing delay case used by Verilog and SDF, such as "assign #(1:2:3) a = b;", whereby 1 is minimum, 2 is typical and 3 is maximum. |
Verilog -> Interconnect Delays |
Specify the delay mode for all interconnect delays. Transport delay mode operates in such a way, that descheduling will not occur for a previously scheduled event that hasn't been realized if a new event is scheduled. Interconnect delays are the time it takes a signal to travel from one module output port to another module input port. |
Verilog -> Path Delays |
Specify the delay mode for all module path delays. Transport delay mode operates in such a way, that descheduling will not occur for a previously scheduled event that hasn't been realized if a new event is scheduled. Module path delays are the time it takes a signal to travel from a module input port through its internal logics to the output port. |
VCD -> Group Bus |
Specify the rendition type for VCD vector nets. |
To add files to a project, select "Project->Add File", here you can select multiple files to add.
Now, before you can start simulation you need to load the simulation, select "Simulation->Load Simulation". After the simulation is loaded, you can start adding breakpoints and waveform objects.
Finally, select "Simulation->Run Simulation", and your simulation will begin.
The hierarchy navigator allows you to browse the design hierarchy. It allows easy navigation through complex design, locating source code line, and adding simulation signals to the waveform viewer. It resembles the "Class View" pane of Microsoft's award-winning IDE Visual Studio 2005, this makes working with complex, multi-file designs a snap.
However, you will not be able to see the design hierarchy until the simulation is loaded..
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The code editor supports syntax highlighting for the following four languages:
- Verilog
- SystemVerilog
- VHDL
- SystemC
It provides basic browsing and editing functionality for source code files.
To create a new Verilog source code file, select "File->New File->Verilog". If a project is open while you create a new source file, the workspace will prompt you to add the file to the project, choose yes to add it to the project, no otherwise.
Once the simulation is loaded, you can start setting simulation breakpoints in a source code file. Not all source code lines are break-able. You can only set breakpoints on lines where the line number is in red color.
The following are Verilog statements which support breakpoint setting:
- Blocking assignment
- Non-blocking assignment
- System task enable
- Task enable
Open up a source code file and locate the line where you wish to set a breakpoint, select "Code->Set/Unset Breakpoint" to set a breakpoint.
Once you're done, select "Simulation->Run Simulation" to continue simulation.
Simulation will be paused when a breakpoint condition is met, at this point you can perform set/unset breakpoints, select "Simulation->Run Simulation" to resume simulation.
To customize the editor, select "Tools->Options->Code Editor ". Editor preferences are saved to a preferences file so you need not re-customize it the next time.
This feature offers the user control over the look-and-feel of the editor.
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The waveform viewer provides a basic means to view waveform signals.
To create a new waveform file, select "File->New File->Waveform". If a project is open while you create a new waveform file, the workspace will prompt you to add the file to the project, choose yes to add it to the project, no otherwise.
In order to dump out simulation waveform, you need to select some signals and save them into a simulation waveform file, and this file needs to be added to the project. To do so, right click on a module instance in the "Hierarchy" pane, select "Add To Waveform":
Signals of the selected module instance will be added to a waveform file on the right-hand side window.
Now run the simulation, select "Simulation->Run Simulation", and the simulation waveform result will be displayed after the simulation is completed. The workspace will prompt you to save the file if it's not yet saved, you must save it as "wave" file extension before you run the simulation, otherwise the waveform result will not be displayed.
To add signals using the object browser, right-click on a signal, select "Add To Waveform".
Signals in the object browser are synchronized with the selected instance in the hierarchy navigator.
To customize the viewer, select "Tools->Options->Waveform Viewer". Viewer preferences are saved to a preferences file so you need not re-customize it the next time.
This feature offers the control over the look-and-feel of the viewer.
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LogicSim also comes in command-line. It is useful for running regression tests, or in a scripted environment. It will offer higher performance throughput and lower memory consumption, when run in command-line.
To use LogicSim in command-line, you must add the installation path to your PATH environment variable, which shall be added by the installer by default. Thereafter, type "lsim" at the command prompt.
The command-line interface allows you to integrate your own IDE software with LogicSim. For greater control and flexibility, we also provide a set of APIs for third-party software tools integration with LogicSim. This will be explained shortly later.
Below is a list of descriptions and basic usage information for every command, or option supported by LogicSim:
| Command | Description |
|---|---|
-f |
This is a compulsory option except when "-api" is used. Specify the input file(s) for the simulation, and you must specify minimum 1 file. There is no limit to the number of files you specify, just separate them with a comma ",". Input file types must be of one of the following file extensions:
e.g. lsim -f file1.v,file2.v -t top |
-w |
This is an optional option. Specify the waveform file(s) for the simulation, and you must specify minimum 1 file. There is no limit to the number of files you specify, just separate them with a comma ",". LogicSim will write to the file(s) you specify, please make sure the file read-only attribute is disabled. Waveform file types must be of one of the following file extensions:
e.g. lsim -f file1.v -t top -w mywave.wave |
-t |
This is an optional option. Specify the top module for the simulation, and you must specify only 1 top module. LogicSim will auto select a top module if no top module is specified. A top-level module is the top most module that instantiates the rest of the modules, and usually do not have any ports, and is also the entry point to the simulation. |
-sim_path |
This is an optional option. Specify the simulation path for the simulation, and you must specify only 1 path. A simulation path is the path used for file I/O and SDF during run-time, e.g. $sdf_annotate, $fopen and so on. The default path is the current working directory if none is specified. |
-sys_path |
This is an optional option. Specify the system path for the simulation, and you must specify only 1 path. A system path is the path used for the system internal and temporary files. The default path is the current working directory if none is specified. Use this option if you do not want LogicSim to create system files in your current working directory. |
-inc_path |
This is an optional option. Specify additional include path(s) for the simulation, and you must specify minimum 1 path. There is not limit to the number of paths you specify, just separate them with a comma ",". An include path is the lookup path used when an include compiler directive such as `include is used. The default path is the current working directory if none is specified. Use this option if you want the compiler to look in additional include path if the include file is not found in your default path. |
-timing_case |
This is an optional option. Specify the timing delay case used by Verilog and SDF, such as "assign #(1:2:3) a = b;", whereby 1 is minimum, 2 is typical and 3 is maximum. The valid argument for this option is "min", "typ" or "max", and you must specify only one argument. The default timing delay case is "typ" if none is specified. |
-int_delays |
This is an optional option. Specify the delay mode for all interconnect delays. Transport delay mode operates in such a way, that descheduling will not occur for a previously scheduled event that hasn't been realized if a new event is scheduled. Interconnect delays are the time it takes a signal to travel from one module output port to another module input port. The valid argument for this option is "inert" or "trans", and you must specify only one argument. The default delay mode is "inert" if none is specified. |
-path_delays |
This is an optional option. Specify the delay mode for all module path delays. Transport delay mode operates in such a way, that descheduling will not occur for a previously scheduled event that hasn't been realized if a new event is scheduled. Module path delays are the time it takes a signal to travel from a module input port through its internal logics to the output port. The valid argument for this option is "inert" or "trans", and you must specify only one argument. The default delay mode is "inert" if none is specified. |
-group_bus |
This is an optional option. Specify the rendition type for VCD vector nets. By default, LogicSim renders vector nets as individual signals, as this is to follow the behavior of ModelSim. For example, "wire [10:1] mywire;" will be rendered as the following if this option is not used: |
-api |
Used for third-party software interfacing over standard I/O communication pipe. The workspace (glsim.exe) communicates with the command-line (lsim.exe) using this option. |
-h |
Display basic command, or option usage information to the standard output stream. In other words, a help screen. |
LogicSim third-party software tool integration can be done by invoking "lsim.exe" with "-api" option.
You can develop your own GUI shell and call Win32 API ::CreateProcess to create a child process of "lsim.exe".
LogicSim relies on the standard I/O stream as communication channels with any third-party software. The workspace (glsim.exe) communicates with the command-line (lsim.exe) this way.
Any scripting mechanism that supports standard I/O stream communication piping, theoratically can communicate with "lsim.exe", e.g. Bash, Perl, Tcl. LogicSim will return "ACK_READY" acknowledgement string to the standard output stream once it's loaded and ready to accept commands.
Every command (API) received will be processed, and in turn return an acknowledgement string back to the output stream, and goes back to waiting mode for the next command from the standard input stream.
The following is further description for each of the LogicSim API:
| API | Description |
|---|---|
API_COMPILE |
Compile the given input files and store the compiled objects in the program memory space. We do not support persistent database at the moment, due to speed and memory reasons. You must specify minimum 1 file. There is no limit to the number of files you specify, just separate them with a comma ",". It will return "ACK_COMPILE 1" acknowledgement string upon success with no errors and "ACK_COMPILE 0" with errors, "ACK_ERROR" otherwise. Input file types must be of one of the following file extensions:
e.g. API_COMPILE file1.v,file2.v |
API_LINK |
Link all compiled objects based on the given top module. You must specify only 1 top module. A top-level module is the top most module that instantiates the rest of the modules, and usually do not have any ports, and is also the entry point to the simulation. It can be used only after "API_COMPILE". It will return "ACK_LINK 1" acknowledgement string upon success with no errors and "ACK_LINK 0 " with errors , "ACK_ERROR" otherwise. |
API_WAVEFORM |
Load the given waveform files for simulation waveform dumping during run-time. You must specify minimum 1 file. There is no limit to the number of files you specify, just separate them with a comma ",". LogicSim will write to the file(s) you specify, please make sure the file read-only attribute is disabled. It can be used only after "API_LINK". It will return "ACK_WAVEFORM" acknowledgement string upon success, "ACK_ERROR" otherwise. Waveform file types must be of one of the following file extensions:
e.g. API_WAVEFORM wave1.wave,wave2.wave |
API_SIMULATE |
Begin simulation given the top module as the entry point. You must specify only 1 top module. A top-level module is the top most module that instantiates the rest of the modules, and usually do not have any ports, and is also the entry point to the simulation. It can be used only after "API_LINK". It will return "ACK_SIMULATE 1" acknowledgement string upon success with no errors and "ACK_SIMULATE 0" with errors, "ACK_ERROR" otherwise. |
API_BUILD_MOD_HIER |
Build module hierarchy tree given the top module as the entry point. You must specify only 1 top module. The output file from this command is <top module>.tree, and it is in readable ASCII text format. The module hierarchy navigator seen in the LogicSim workspace is created using this API. It can be used only after "API_LINK". It will return "ACK_BUILD_MOD_HIER" acknowledgement string upon success, "CMD_ERROR" otherwise. |
API_BUILD_OBJ |
Build module hierarchy tree objects starting from the given top module as the entry point, e.g. variables, parameters, registers, etc. You must specify only 1 top module. The output file from this command is <top module>.obj, and it is in readable ASCII text format. Example, it can be seen when right-click on a module instance in the module hierarchy navigator and selecting "Add To Waveform", whereby all signals of the module instance are dumped to the waveform viewer. It can be used only after "API_LINK". It will return "API_BUILD_OBJ" acknowledgement string upon success, "API_ERROR" otherwise. |
API_SET_OPTION |
Set a simulation option, e.g. transport delays, delay switch, include paths, etc. You must specify only 1 option at a time. It will return "ACK_SET_OPTION" acknowledgement string upon success, "ACK_ERROR" otherwise. |
API_SET_BP |
Set a simulation breakpoint given the file name, line number, and condition. You must specify the file name and the line number, whereby the condition is optional. It can be used only after "API_LINK", or when the simulation session is paused, e.g. after a breakpoint is asserted. It will return "ACK_SET_BP" acknowledgement string upon success, "ACK_ERROR" otherwise. |
API_UNSET_BP |
Unset a simulation breakpoint given the file name and line number. It can be used only after "API_LINK", or when the simulation session is paused, e.g. after a breakpoint is asserted. It will return "ACK_UNSET_BP" acknowledgement string upon success, "ACK_ERROR" otherwise. |
API_EXIT |
Terminate API communication session regardless simulation has been started or not. It will return "ACK_EXIT" acknowledgement string upon success, "ACK_ERROR" otherwise. |
This set of API is growing from time to time, come back and check for new updates often. This is not meant to replace Verilog PLI, and we do have plans to support Verilog PLI very soon.
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The following is a list of Verilog System Functions/Tasks currently supported by LogicSim. Please note that some of them are not defined in the Verilog IEEE 1364-2001 LRM, rather they're supported for the convenience of the users. Please refer to Verilog-2001 LRM for complete usage information for each of them.
| Name | Description |
|---|---|
|
$bits
|
Return the size of a variable in terms the number of bits |
|
$bitstoreal
|
Convert a stream of bits to a real value |
|
$deposit
|
Value assigment |
|
$display
|
Display formatted string to the standard output stream, defaulted to decimal values |
|
$displayb
|
Display formatted string to the standard output stream, defaulted to binary values |
|
$displayh
|
Display formatted string to the standard output stream, defaulted to hex values |
|
$displayo
|
Display formatted string to the standard output stream, defaulted to octal values |
|
$dist_chi_square
|
Chi square distribution |
|
$dist_erlang
|
Erlang distribution |
|
$dist_exponential
|
Exponential distribution |
|
$dist_normal
|
Normal distribution |
|
$dist_poisson
|
>Poisson distribution |
|
$dist_t
|
T distribution |
|
$dist_uniform
|
Uniform distribution |
|
$dumpall
|
Same as $dumpvars |
|
$dumpfile
|
Specify the name of the VCD dump file |
|
$dumpflush
|
Flush out all pending VCD updates to the file |
|
$dumpoff
|
Disable VCD dumping during simulation |
|
$dumpon
|
Enable VCD dumping during simulation, default is on |
|
$dumpvars
|
Specify the objects you wish to dump for VCD |
|
$fclose
|
Close an open file given the file handler |
|
$fdisplay
|
Display formatted string to a file output stream, defaulted to decimal values |
|
$fdisplayb
|
Display formatted string to a file output stream, defaulted to binary values |
|
$fdisplayh
|
Display formatted string to a file output stream, defaulted to hex values |
|
$fdisplayo
|
>Display formatted string to a file output stream, defaulted to octal values |
|
$feof
|
Return 1 if EOF is reached, 0 otherwise |
|
$fflush
|
Flush out file I/O operations |
|
$fgetc
|
Get a single character from the file input stream |
|
$fgets
|
Get a string from the file input stream, whitespace terminates reading |
|
$finish
|
End the simulation session |
|
$fmonitor
|
Monitor simulation signals, and write to a file output stream, defaulted to decimal values |
|
$fmonitorb
|
Monitor simulation signals, and write to a file output stream, defaulted to binary values |
|
$fmonitorh
|
Monitor simulation signals, and write to a file output stream, defaulted to hex values |
|
$fmonitoro
|
Monitor simulation signals, and write to a file output stream, defaulted to octal values |
|
$fopen
|
Open a file for I/O operations > |
|
$fread
|
Perform file I/O reading operations |
|
$fscanf
|
Perform file I/O formated reading operations |
|
$fseek
|
Position the file pointer to a specific location in the file |
|
$fstrobe
|
Same as $fdisplay, but update happens at the end of simulation cycle |
|
$fstrobeb
|
Same as $fdisplayb, but update happens at the end of simulation cycle |
|
$fstrobeh
|
Same as $fdisplayh, but update happens at the end of simulation cycle |
|
$fstrobeo
|
Same as $fdisplayo, but update happens at the end of simulation cycle |
|
$ftell
|
Return the current file pointer location in the file |
|
$fwrite
|
Similar to $fdisplay, except will not format the output |
|
$fwriteb
|
Similar to $fdisplayb, except will not format the output |
|
$fwriteh
|
Similar to $fdisplayh, except will not format the output |
|
$fwriteo
|
Similar to $fdisplayo, except will not format the output |
|
$getpattern
|
Return a value from the argument |
|
$itor
|
Convert an integer value to a real value |
|
$monitor
|
Monitor simulation signals, and write to the standard output stream, defaulted to decimal values |
|
$monitorb
|
Monitor simulation signals, and write to the standard output stream, defaulted to binary values |
|
$monitorh
|
Monitor simulation signals, and write to the standard output stream, defaulted to hex values |
|
$monitoro
|
Monitor simulation signals, and write to the standard output stream, defaulted to octal values |
|
$monitoroff
|
Disable signal monitoring during simulation |
|
$monitoron
|
Enable signal monitoring during simulation, default is on |
|
$printtimescale
|
Print the time scale used by the current module |
|
$random
|
Return a psuedo random number |
|
$readmemb
|
Read binary values from a text file, and assign them to a memory variable |
|
$readmemh
|
Read hex values from a text file, and assign them to a memory variable |
|
$realtime
|
Return the current simulation time as real value |
|
$realtobits
|
Convert a real value to a stream of bits |
|
$rewind
|
Position the file pointer to the starting location in the file |
|
$rtoi
|
Convert a real value to an integer value |
|
$sdf_annotate
|
Annotate timing information from an SDF file to the current simulation |
|
$sformat
|
Return a formated string |
|
$signed
|
>Convert an unsigned value to a signed value |
|
$sizeof
|
Return the size of a variable |
|
$sprintf
|
Return a formated string |
|
$sscanf
|
Perform formated string assignment |
|
$stime
|
Same as $time |
|
$strobe
|
Same as $display, but update happens at the end of simulation cycle |
|
$strobeb
|
Same as $displayb, but update happens at the end of simulation cycle |
|
$strobeh
|
Same as $displayh, but update happens at the end of simulation cycle |
|
$strobeo
|
Same as $displayo, but update happens at the end of simulation cycle |
|
$stop
|
Stop the current simulation session |
|
$time
|
Return the current simulation time |
|
$timeformat
|
Format %t display specifier |
|
$ungetc
|
Unget a single character from the file input stream |
|
$unsigned
|
Convert an unsigned value to a signed value |
|
$write
|
Similar to $display, except will not format the output |
|
$writeb
|
Similar to $displayb, except will not format the output |
|
$writeh
|
Similar to $displayh, except will not format the output |
|
$writeo
|
Similar to $displayo, except will not format the output |
|
$writememb
|
Write binary values from a memory to a text file |
|
$writememh
|
Write hex values from a memory to a text file |
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Decimal radix conversion on vector size > 64-bit will be ignored, as we can only support radix conversion to decimal for up to 64-bit currently. On the other hand, there's no bit size limit to other radix conversions, such as hex, octal, ascii and so on.
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Only single dimension array is supported at the moment, whereas arrays with more than 1 dimensions are not supported.
reg [10:1] myarray [10:1]; // <--- this is supported
reg [10:1] myarray [10:1][10:1]; // <--- this is NOT supported
Actually, multi-dimension arrays are rarely used in real world models, somehow we will still support this in the future.
We do not currently support any application programming interface defined by the LRM standard. As we find the API standard is huge, and it only benefits third-party software integration, hence support priority is given to more important features at the moment. We might consider supporting this in the future if it's still relevant, as DPI is a new simulator API in SystemVerilog.
If you'd still like to integrate your software with LogicSim, you may want to try our proprietary API, unfortunately it's far from comprehensive at the moment. Click here for details.
