LogicSim is an affordable and user-friendly Verilog simulator for ASIC and FPGA design verification. It offers a powerful and easy-to-use graphical user interface that lets you quickly simulate your Verilog designs. It's built on our state-of-the-art single kernel simulation engine MULCORED™ (Multi-Core Event Distribution) technology.
WaveProbe is a waveform viewer useful for examining the output of various logic simulators (like LogicSim, ModelSim, VCS). It offers a powerful and easy-to-use graphical user interface that lets you quickly analyze and debug your waveform files. It currently supports VCD/EVCD and LogicSim waveform output formats.News
- Altera's Stratix III FPGAs Support SGMII on LVDS I/Os
Stratix III FPGAs are the industry's first programmable logic devices able to support Gigabit Ethernet SGMII on LVDS pins, offering lower costs, lower power and more interfaces per device. more... - eASIC Issues $30,000 Worldwide Placement Design Challenge
eASIC will offer a total prize of $30,000 to the individuals or groups that can implement the most efficient placement algorithms. more...
Customer Praise
LogicSim is an excellent
product. I've been able to proficiently use it from the moment I ran it
the first time. The most user-friendly Verilog simulator I have ever seen.
Tutorials
- A Simple "Hello World!" Simulation
Help you create a simple "Hello World!" simulation in Verilog using LogicSim. - Creating a Simulation Project
Help you create a simple simulation project. This project will display a simple "Hello World!" text when simulated. - Adding Signals to Waveform Viewer from Hierarchy Navigator
Help you dump simulation signals to the waveform viewer for debugging from the hierarchy navigator.
